ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |8-12 years| Pune)
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ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |8-12 years| Pune)
Pune, Maharashtra
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Experience
8+ yrs
Salary
Not disclosed
Job type
Full-time
Openings
1
Education
Any graduate
Apply by
22 Oct 2026
Cisco’s Client Optics Group (COG) designs and delivers the high-speed optical transceivers and platforms that power Cisco's core data center networking solutions, specializing in cutting-edge IM/DD optics and silicon photonic platforms.
- Lead ASIC design verification for high-speed optical transceivers and silicon photonic platforms
- 8-12 years of relevant experience in ASIC design verification
- Proficiency in SystemVerilog, Python, C, and UVM
Skills
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